Sun Chen

National University of Singapore (NUS)

Publications

2023

  1. D. Zhang, J. Wu, Q. Kong, Z. Zhou, L. Liu, K. Han, C. Sun, X. Wang, G. Liu, L. Jiao, Z. Zheng, Y. Kang, J. Chen, and X. Gong, “Grain size reduction of ferroelectric HZO enabled by a novel solid phase epitaxy (SPE) approach: Working principle, experimental demonstration, and theoretical understanding,” in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2023, pp. T12-1. (Accepted)
  2. Z. Zheng, L. Jiao, Z. Zhou, Y. Wang, L. Liu, K. Han, C. Sun, Q. Kong, D. Zhang, X. Wang, K. Ni, and X. Gong, “First demonstration of work function-engineered BEOL-compatible IGZO non-volatile MFMIS AFeFETs and their co-integration with volatile-AFeFETs,” in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2023, pp. T12-2. (Accepted)
  3. Z. Zhou, L. Jiao, Q. Kong, Z. Zheng, K. Han, Y. Chen, C. Sun, B.-Y. Nguyen, and X. Gong, “Non-destructive-read 1T1C ferroelectric capacitive memory cell with BEOL 3D monolithically integrated IGZO access transistor for 4F2 high-density integration,” in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2023, pp. TFS1-3. (Accepted)
  4. X. Wang, Z. Zheng, Q. Kong, L. Jiao, K. Han, C. Sun, Z. Zhou, L. Liu, Y. Kang, G. Liu, D. Zhang, and X. Gong, “First demonstration of BEOL-compatible MFMIS Fe-FETs with 3D multi-fin floating gate: In-situ ALD-deposited MFM, LCH of 50 nm, > 2×109 endurance, and 58.3% area saving,” in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2023, pp. T5-4. (Accepted)
  5. J. Zhang, H. Xu, Q. Kong, C. Sun, and X. Gong, “Flexible InGaAs avalanche photodiode,” No. 10202301358P, TTI Ref: 2023-045-01. (SG Patent)
  6. L. Xu, J. Guo, C. Sun, Z. Zheng, Y. Xu, S. Huang, K. Han, W. Wei, Z. Guo, X. Gong, Q. Luo, L. Wang, and L. Li, “A surface potential based compact model for ferroelectric a-InGaZnO-TFTs towards temperature dependent device characterization,” IEEE Electron Device Letters, vol. 44, no. 3, pp. 412–415, Mar. 2023.
  7. J. Zhang, H. Xu, G. Zhang, Y. Chen, H. Wang, K. H. Tan, S. Wicaksono, C. Sun, Q. Kong, C. Wang, C. C. W. Lim, S.-F. Yoon, and X. Gong, “Hybrid and heterogeneous photonic integrated near-infrared InGaAs/InAlAs single-photon avalanche diode,” Quantum Sci. Technol., vol. 8, no. 2, p. 025009, Feb. 2023.
  8. Q. Kong, L. Liu, Z. Zheng, C. Sun, Z. Zhou, L. Jiao, A. Kumar, R. Shao, J. Zhang, H. Xu, Y. Chen, B.-Y. Nguyen, and X. Gong, “Back-end-of-line-compatible fin-gate ZnO ferroelectric field-effect transistors,” IEEE Transactions on Electron Devices, pp. 1–8, 2023.

2022

  1. B. Nguyen, C. Maleville, W. Schwarzenbach, G. Xiao, A. Thean, C. Sun, and H. Xu, “Device architectures with tensile and compressive strained substrates,” 20220399441, Dec. 15, 2022. (US Patent)
  2. C. Sun, X. Wang, H. Xu, J. Zhang, Z. Zheng, Q. Kong, Y. Kang, K. Han, L. Jiao, Z. Zhou, Y. Chen, D. Zhang, G. Liu, L. Liu, and X. Gong, “Novel a-IGZO anti-ferroelectric FET LIF neuron with co-integrated ferroelectric FET synapse for spiking neural networks,” in 2022 IEEE International Electron Devices Meeting (IEDM), Dec. 2022, p. 2.1.1-2.1.4.
  3. X. Wang*, C. Sun*, Z. Zheng, L. Jiao, Z. Zhou, D. Zhang, G. Liu, Q. Kong, J. Zhang, H. Xu, K. Han, Y. Kang, L. Liu, and X. Gong, “Deep insights into the interplay of polarization switching, charge trapping, and soft breakdown in metal-ferroelectric-metal-insulator-semiconductor structure: Experiment and modeling,” in 2022 IEEE International Electron Devices Meeting (IEDM), Dec. 2022, p. 13.3.1-13.3.4. (Co-First Author)
  4. Q. Kong, L. Liu, Z. Zheng, C. Sun, A. Kumar, R. Shao, Z. Zhou, L. Jiao, J. Zhang, H. Xu, Y. Chen, G. Liu, D. Zhang, X. Wang, B.-Y. Nguyen, and X. Gong, “First demonstration of BEOL-compatible 3D Fin-gate oxide semiconductor Fe-FETs,” in 2022 IEEE International Electron Devices Meeting (IEDM), Dec. 2022, p. 12.3.1-12.3.4.
  5. Q. Kong, G. Liu, C. Sun, Z. Zheng, D. Zhang, J. Zhang, H. Xu, L. Liu, Z. Zhou, L. Jiao, X. Wang, K. Han, Y. Kang, B.-Y. Nguyen, K. Ni, and X. Gong, “New insights into the impact of hydrogen evolution on the reliability of IGZO FETs: Experiment and modeling,” in 2022 IEEE International Electron Devices Meeting (IEDM), Dec. 2022, p. 30.2.1-30.2.4.
  6. X. Gong, K. Han, C. Sun, Z. Zheng, Q. Kong, Y. Kang, C. Wang, A. Kumar, Z. Zhou, L. Jiao, and L. Liu, “BEOL-compatible InGaZno-based devices for 3D integrated circuits,” Meet. Abstr., vol. MA2022-02, no. 32, p. 1186, Oct. 2022, doi: 10.1149/MA2022-02321186mtgabs.
  7. C. Sun, C. Li, S. Samanta, K. Han, Z. Zheng, J. Zhang, Q. Kong, H. Xu, Z. Zhou, Y. Chen, C. Zhuo, K. Ni, X. Yin, and X. Gong, “Computational associative memory with amorphous metal-oxide channel 3D NAND-compatible floating-gate transistors,” Advanced Electronic Materials, p. 2200643, Sep. 2022.
  8. C. Sun, K. Han, S. Samanta, Q. Kong, J. Zhang, H. Xu, X. Wang, A. Kumar, C. Wang, Z. Zheng, X. Yin, K. Ni, and X. Gong, “Highly scaled InGaZnO ferroelectric field-effect transistors and ternary content-addressable memory,” IEEE Transactions on Electron Devices, vol. 69, no. 9, pp. 5262–5269, Sep. 2022.
  9. L. Jiao, Z. Zhou, Z. Zheng, Y. Kang, C. Sun, Q. Kong, X. Wang, D. Zhang, G. Liu, L. Liu, and X. Gong, “BEOL-compatible Ta/HZO/W ferroelectric tunnel junction with low operating voltage targeting for low power application,” in 2022 International Conference on IC Design and Technology (ICICDT), Sep. 2022, pp. 5–7.
  10. Z. Zheng, C. Sun, L. Jiao, D. Zhang, Z. Zhou, X. Wang, G. Liu, Q. Kong, Y. Chen, K. Ni, and X. Gong, “Boosting the memory window of the BEOL-compatible MFMIS ferroelectric/anti-ferroelectric FETs by charge injection,” in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2022, pp. 389–390.
  11. J. Zhang, H. Xu, K. H. Tan, S. Wicaksono, Q. Kong, G. Zhang, Y. Chen, C. Sun, H. Wang, C. Wang, Z. Zheng, L. Jiao, Z. Zhou, C. C. W. Lim, S.-F. Yoon, and X. Gong, “First Si-waveguide-integrated InGaAs/InAlAs avalanche photodiodes on SOI platform,” in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2022, pp. 409–410.
  12. C. Wang, A. Kumar, K. Han, C. Sun, H. Xu, J. Zhang, Y. Kang, Q. Kong, Z. Zheng, Y. Wang, and X. Gong, “Extremely scaled bottom gate a-IGZO transistors using a novel patterning technique achieving record high Gm of 479.5 μS/μm (VDS of 1 V) and fT of 18.3 GHz (VDS of 3 V),” in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2022, pp. 294–295.
  13. Y. Chen, G. Zhang, J. Zhou, Z. Zheng, L. Jiao, H. Wang, Z. Zhou, A. Kumar, J. Zhang, Y. Wang, Q. Kong, C. Sun, and X. Gong, “First demonstration of fully CMOS-compatible non-volatile programmable photonic switch enabled by ferroelectric-SOI waveguide for next generation photonic integrated circuit,” in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2022, pp. 405–406.
  14. J. Liang*, C. Sun*, H. Xu, E. Y.-J. Kong, B.-Y. Nguyen, W. Schwarzenbach, C. Maleville, R. Berthelon, O. Weber, F. Arnaud, A. V.-Y. Thean, and X. Gong, “Strained silicon-on-insulator platform for co-integration of logic and RF—Part II: Comb-like device architecture,” IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 1769–1775, Apr. 2022. (Co-First Author)
  15. Q. Kong, C. Sun, Z. Zheng, Z. Zhou, L. Jiao, K. Han, Y. Kang, J. Zhang, H. Xu, Y. Chen, and X. Gong, “Understanding positive bias stability of a-InGaZnO thin film transistors with HfO2 gate dielectric using fast measurement techniques,” in 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Apr. 2022, pp. 1–2.

2021

  1. C. Sun, Z. Zheng, K. Han, S. Samanta, J. Zhou, Q. Kong, J. Zhang, H. Xu, A. Kumar, C. Wang, and X. Gong, “Temperature-dependent operation of InGaZnO ferroelectric thin-film transistors with a metal-ferroelectric-metal-insulator-semiconductor structure,” IEEE Electron Device Letters, vol. 42, no. 12, pp. 1786–1789, Dec. 2021.
  2. J. Liu*, C. Sun*, W. Tang, Z. Zheng, Y. Liu, H. Yang, C. Jiang, K. Ni, X. Gong, and X. Li, “Low-power and scalable retention-enhanced IGZO TFT eDRAM-based charge-domain computing,” in 2021 IEEE International Electron Devices Meeting (IEDM), Dec. 2021, p. 21.1.1-21.1.4. (Co-First Author)
  3. K. Han, Q. Kong, Y. Kang, C. Sun, C. Wang, J. Zhang, H. Xu, S. Samanta, J. Zhou, H. Wang, A. V.-Y. Thean, and X. Gong, “Indium-gallium-zinc-oxide (IGZO) nanowire transistors,” IEEE Transactions on Electron Devices, vol. 68, no. 12, pp. 6610–6616, Dec. 2021.
  4. Z. Zhou, L. Jiao, J. Zhou, Q. Kong, S. Luo, C. Sun, Z. Zheng, X. Wang, D. Zhang, G. Liu, G. Liang, and X. Gong, “Time-dependent Landau-Ginzburg equation-based ferroelectric tunnel junction modeling with dynamic response and multi-domain characteristics,” IEEE Electron Device Letters, vol. 43, no. 1, pp. 158–161.
  5. Y. Kang, K. Han, A. Kumar, C. Wang, C. Sun, Z. Zhou, J. Zhou, and X. Gong, “Back-end-of-line compatible fully depleted CMOS inverters employing Ge p-FETs and α-InGaZnO n-FETs,” IEEE Electron Device Letters, vol. 42, no. 10, pp. 1488–1491.
  6. K. Han, S. Samanta, C. Sun, and X. Gong, “Top-gate short channel amorphous indium-gallium-zinc-oxide thin film transistors with sub-1.2 nm equivalent oxide thickness,” IEEE Journal of the Electron Devices Society, vol. 9, pp. 1125–1130, Sep. 2021.
  7. J. Zhang, H. Xu, G. Zhang, Y. Chen, H. Wang, K. H. Tan, S. Wicaksono, C. Wang, C. Sun, Q. Kong, C. C. W. Lim, S.-F. Yoon, and X. Gong, “First InGaAs/InAlAs single-photon avalanche diodes (SPADs) hetero integrated with Si photonics on SOI platform for 1550 nm detection,” in 2021 Symposium on VLSI Technology, Jun. 2021, pp. 1–2.
  8. H. Xu, X. Wang, S. Luo, J. Zhang, K. Han, C. Sun, C. Wang, R. Khazaka, Q. Xie, Y. Huang, Y. Zhou, J. He, G. Liang, and X. Gong, “Ultra-low specific contact resistivity (3.2×10-10 Ω-cm2) of Ti/Si0.5Ge0.5 contact: Deep insights into the role of interface reaction and Ga co-doping,” in 2021 Symposium on VLSI Technology, Jun. 2021, pp. 1–2.
  9. C. Sun, K. Han, S. Samanta, Q. Kong, J. Zhang, H. Xu, X. Wang, A. Kumar, C. Wang, Z. Zheng, X. Yin, K. Ni, and X. Gong, “First demonstration of BEOL-compatible ferroelectric TCAM featuring a-IGZO Fe-TFTs with large memory window of 2.9 V, scaled channel length of 40 nm, and high endurance of 108 cycles,” in 2021 Symposium on VLSI Technology, Jun. 2021, pp. 1–2.
  10. K. Han, Q. Kong, Y. Kang, C. Sun, C. Wang, J. Zhang, H. Xu, S. Samanta, J. Zhou, H. Wang, A. V.-Y. Thean, and X. Gong, “First demonstration of oxide semiconductor nanowire transistors: a novel digital etch technique, IGZO channel, nanowire width down to 20 nm, and Ion exceeding 1300 μA/μm,” in 2021 Symposium on VLSI Technology, Jun. 2021, pp. 1–2.
  11. J. Zhang, H. Wang, G. Zhang, H. Xu, K. H. Tan, S. Wicaksono, C. Wang, T. Ren, C. Sun, Y. Chen, Y. Liang, C. C. Wen Lim, S.-F. Yoon, and X. Gong, “Triple-mesa InGaAs/InAlAs single-photon avalanche diode array for 1550 nm photon detection,” in 2021 Conference on Lasers and Electro-Optics (CLEO), May 2021, pp. 1–2.
  12. C. Sun, H. Xu, J. Liang, E. Y.-J. Kong, B.-Y. Nguyen, W. Schwarzenbach, C. Maleville, R. Berthelon, O. Weber, F. Arnaud, X. Wang, A. V.-Y. Thean, and X. Gong, “Strained Silicon-on-Insulator Platform for Cointegration of Logic and RF—Part I: Implant-Induced Strain Relaxation,” IEEE Transactions on Electron Devices, vol. 68, no. 4, pp. 1425–1431, Apr. 2021.
  13. K. Han, S. Samanta, C. Sun, J. Zhang, Z. Zheng, and X. Gong, “Top-gate short channel amorphous indium-gallium-zinc-oxide thin film transistors with sub-1.2 nm equivalent oxide thickness,” in 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Apr. 2021, pp. 1–3.
  14. S. Samanta, K. Han, C. Sun, C. Wang, A. Kumar, A. V.-Y. Thean, and X. Gong, “Amorphous InGaZnO thin-film transistors with sub-10-nm channel thickness and ultrascaled channel length,” IEEE Transactions on Electron Devices, vol. 68, no. 3, pp. 1050–1056, Mar. 2021.

2020

  1. K. Han, C. Sun, E. Y. J. Kong, Y. Wu, C.-H. Heng, and X. Gong, “Hybrid design using metal-oxide-semiconductor field-effect transistors and negative-capacitance field-effect transistors for analog circuit applications,” IEEE Transactions on Electron Devices, vol. 68, no. 2, pp. 846–852, Dec. 2020.
  2. Z. Zhou, J. Zhou, X. Wang, H. Wang, C. Sun, K. Han, Y. Kang, Z. Zheng, H. Ni, and X. Gong, “A metal-insulator-semiconductor non-volatile programmable capacitor based on a HfAlOx ferroelectric film,” IEEE Electron Device Letters, vol. 41, no. 12, pp. 1837–1840, Dec. 2020.
  3. J. Zhou, Z. Zhou, X. Wang, H. Wang, C. Sun, K. Han, Y. Kang, and X. Gong, “Temperature dependence of ferroelectricity in Al-doped HfO2 featuring a high Pr of 23.7 μC/cm2,” IEEE Transactions on Electron Devices, vol. 67, no. 12, pp. 5633–5638, Dec. 2020.
  4. J. Zhou, Z. Zhou, X. Wang, H. Wang, C. Sun, K. Han, Y. Kang, and X. Gong, “Demonstration of ferroelectricity in Al-doped HfO2 with a low thermal budget of 500 °C,” IEEE Electron Device Letters, vol. 41, no. 7, pp. 1130–1133, Jul. 2020.
  5. C. Sun, J. Liang, H. Xu, E. Kong, B.-Y. Nguyen, A. Vandooren, W. Schwarzenbach, C. Maleville, V. Barral, R. Berthelon, O. Weber, F. Arnaud, A. V. Y. Thean, and X. Gong, “Enabling UTBB strained SOI platform for co-integration of logic and RF: Implant-induced strain relaxation and comb-like device architecture,” in 2020 IEEE Symposium on VLSI Technology, Jun. 2020, pp. 1–2.
  6. S. Samanta, K. Han, C. Sun, C. Wang, A. V.-Y. Thean, and X. Gong, “Amorphous IGZO TFTs featuring extremely-scaled channel thickness and 38 nm channel length: Achieving record high Gm,max of 125 μS/μm at VDS of 1 V and ION of 350 μA/μm,” in 2020 IEEE Symposium on VLSI Technology, Jun. 2020, pp. 1–2.

2019

  1. Y. Wu, H. Xu, L.-H. Chua, K. Han, W. Zou, T. Henry, J. Zhang, C. Wang, C. Sun, and X. Gong, “A novel fast-turn-around ladder TLM methodology with parasitic metal resistance elimination, and 2×10-10 Ω-cm2 resolution: Theoretical design and experimental demonstration,” in 2019 Symposium on VLSI Technology, Jun. 2019, pp. T150–T151.
  2. K. Han, Y. Wu, Y. C. Huang, S. Xu, A. Kumar, E. Kong, Y. Kang, J. Zhang, C. Wang, H. Xu, C. Sun, and X. Gong, “First demonstration of complementary FinFETs and tunneling FinFETs co-integrated on a 200 mm GeSnOI substrate: A pathway towards future hybrid nano-electronics systems,” in 2019 Symposium on VLSI Technology, Jun. 2019, pp. T182–T183.
  3. C. Sun, K. Han, and X. Gong, “Performance evaluation of static random access memory (SRAM) based on negative capacitance FinFET,” in 2019 International Conference on IC Design and Technology (ICICDT), Jun. 2019, pp. 1–4. (Best Paper Award)